System and method for column access in random access memories
US6279071A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 7, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Jul 7, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A column access system is provided with a column counter for producing a column address in response to an external address. The column address is latched in an address decoder which decodes the column address to select a column in the DRAM. A command decoder generates a column decode enable signal supplied to the address decoder to control latching of the column address, and a write enable signal, together with data, supplied to a write driver. A data latch is provided in the write driver for latching data until an equalize control signal is activated. The latched data signal drives global input/output pair to provide data writing to the DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.