Apparatus and method for synchronizing a cache mode in a dual controller, dual cache memory system operating in a plurality of cache modes
US6279078A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1996 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Jun 28, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for synchronizing a cache mode in a cache memory system in a computer to protect cache operations. The cache memory system has a first controller and a second controller and two cache modules and operates in a plurality of cache modes. The cache mode is stored as metadata in the cache modules and is detected by the first controller to determine the cache mode. Lock signals in the first controller are set in accordance with the cache mode detected to set the cache mode state in the first controller. The second controller copies the cache mode state from the first controller to synchronize both controllers in the same cache mode state. After a failure of the second controller, the first controller may lock access to both caches to recover data previously accessed by the second controller. The second controller restarts and copies the cache mode state from the first controller, so that both controllers return to the cache mode state prior to the failure of the second controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.