Method and apparatus for association of memory locations with a cache location having a flush buffer
US6279080A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 9, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Jun 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for associating memory locations with cache locations includes processing that begins by receiving a request for access to a memory block of memory from one of a plurality of clients. A client may be a host processor, a video graphics processor, or an application running on a host processor or video graphics processor. The processing continues by determining whether a physical cache address associated with the memory block is identified in a flush buffer when the memory block is not currently allocated a logical cache address. The logical cache address is utilized by the system memory controller to allocate a physical cache address of the cache to the memory block. The flush buffer contains addresses of physical cache locations that have been identified to be flushed back to the memory, but are not directly accessible by the host processor since the logical address allocation has been deleted. The processing continues by allocating one of the plurality of logic cache addresses to the memory block when the physical cache address is identified in the flush buffer. The processing then continues by associating the one of the plurality of logical cache addresses w…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.