Circuit and method of controlling cache memory
US6279083A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 24, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Mar 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller (26) compares the current address and the previous address sent by a microprocessor (12). If the addresses are DRAM addresses and the current row address matches the previous row address, i.e. same DRAM page access, then the memory controller disables caching (28) of the same DRAM page access. The same DRAM page access disables caching because the same DRAM page access is not substantially longer than a cache access. A counter (50) and comparator (52) allows the memory controller to hold off some number of same DRAM page accesses before disabling caching to give time for the memory controller to set up to the new page.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.