Digital signal processing memory logic unit using PLA to modify address and data bus output values
US6279096A · kind A · utility
8Cited by
0References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Oct 1, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The inventive system and method provides a processing resource which performs bit reversing and Boolean algebraic operations. These operations are commonly needed by discrete transform algorithms to reorder data samples. By selectively remapping the address bus, a series of non-linear accesses to the data memory are converted to linear accesses. Another use of the invention to pack floating point numbers in memory is also disclosed. An embodiment using an in-circuit reprogrammable logic device is disclosed which allows processing software to dynamically reconfigure the mapping logic and rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.