Method and apparatus for significantly improving the reliability of multilevel memory architecture
US6279133A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1998 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Oct 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5642
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for significantly improving the reliability of multilevel (MLT) memory architecture. Before writing to MLT architecture, each MLT word is encoded into a coded bit stream in such a way that the resultant coded data contains the original word plus additional digits which are a function of the content of memory. During the reading of the memory, the stored data is decoded, and takes advantage of redundancy to correct and eliminate errors introduced during read and write operations of the MLT architecture. The invention is useful for systems such as general-purpose computers (PCs, workstations, etc.), telecommunications devices (telephones--wired and wireless, switches, hubs, routers, etc.), audio and visual devices (recording and playback, editing, format switching, compression, etc.), vehicles (automobiles, aircraft, trains, boats, satellites, spacecraft, etc.). Systems and subsystems may be incorporated on a single integrated circuit (IC) die having MLT RAM or enhanced MLT memory. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.