Apparatus and method for verifying a multi-component electronic design
US6279146A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1999 |
| Grant date | Aug 21, 2001 |
| Priority date | — |
| Expiry date | Jun 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A verification engine for verifying the design of a target system having a plurality of components interconnected by a plurality of target system buses is disclosed. The verification engine comprises a first hardware model and a second hardware model, both configured as a component and having a set of hardware model input/output pins. In addition, a first bus wrapper is connected to the first hardware model and a second bus wrapper is connected to the second hardware model. Further, a set of bus lines are each connected to the first bus wrapper and the second bus wrapper. Each bus wrapper also has switchable communicative circuitry that switchably communicatively connects each hardware model input/output pin to a bus line and has a control block controlling the switchable communicative circuitry. A system controller is connected to at least some of the bus lines and is adapted to transmit a sequence of time synchronization information to each bus wrapper control block by way of the bus lines. Finally, responsive to a predetermined one of the time slot numbers both of the control blocks switch at least one input/output pin into communicative contact with a the bus line so that at le…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.