System and method to provide power to a sea of gates standard cell block from an overhead bump grid
US6281108A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 15, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Oct 15, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system and method for providing power to the gates of a semiconductor chip routes power and ground from one layer of the chip to another layer of the chip using a first metal strip located at a first metal layer and a second metal strip located at a second metal layer, wherein the second metal layer is not directly adjacent to the first metal layer. A stacked via is used to connect the first metal strip to the second metal strip. The stacked via may comprise, for example, a first via connecting the first metal strip to an intermediate metal strip and a second via connecting the intermediate metal strip to the second metal strip. Alternatively, the stacked via may comprise a plurality of vias connecting the first metal strip to the intermediate metal strip and a plurality of vias connecting the intermediate metal strip to the second metal strip. The system and method avoids using long, parallel metal strips on each layer of the chip to route power and ground from one layer of the chip to another layer of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.