Semiconductor memory device having bitlines of common height
US6281540A · kind A · utility
22Cited by
10References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 25, 1998 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Feb 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/482
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a memory cell region having an array of plurality of memory cells, and a peripheral circuit region to which a bit line connected to a predetermined number of the memory cells in the memory cell region is extended and connected, the bit line in the memory cell region and the bit line in the peripheral circuit region having substantially the same upper surface height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.