Power efficient line driver
US6281747A · kind A · utility
14Cited by
12References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2001 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Jan 24, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/331
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A signal processing circuit is described including a frequency selective network in a feedback loop. An analog-to-analog converter in the feedback loop is coupled to the frequency selective network. A continuous-time feedback path provides feedback from the output terminal of the analog-to-analog converter to the frequency selective network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.