Moire cancellation circuit
US6281889A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 1998 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Mar 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/68
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit (300) for reducing Moire effects in a display by delaying in alternate horizontal display lines a received horizontal drive pulse (HDRV IN), the circuit having: a current source arrangement (304, 314.1-314.n, 316.1-316.n) for tracking the display scanning speed and for producing a current which is representative of a binary input value (DVAL); a capacitor (308) arranged to be charged by the current; and a comparator (310) connected to the capacitor for delaying the received horizontal drive pulse by an amount dependent on the rate of charging of the capacitor. The circuit provides auto tracking with display scanning speed and programmability of the delay value. The circuit can be fabricated in integrated circuit form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.