SRAM method and apparatus
US6282137A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Sep 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is a method and apparatus for minimizing voltage swing on the BIT and BIT lines of a static random access memory (SRAM), thus minimizing precharge time and READ time for the SRAM. In accordance with the invention, an enhanced sense amplifier is provided in the last column of the memory array. The enhanced sense amplifier detects when the differential voltage between the BIT and BIT lines exceeds the minimum detectable threshold of the sense amplifier. In response to that event, it asserts a feedback line to the READ control circuitry which halts the read operation essentially as soon as the differential voltage between the BIT and BIT lines reaches the minimum differential voltage detectable by the sense amplifier. The technique is adaptive and assures both accurate operation and minimal precharge and read access times across variations in temperature and other environmental conditions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.