Multiplexor having a single event upset (SEU) immune data keeper circuit
US6282140A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 8, 2000 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Jun 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplexor having a single event upset (SEU) hardened data keeper circuit is disclosed. The multiplexor includes a precharge transistor, an isolation transistor, an invertor, and an SEU immune storage cell. Both the gate of the precharge transistor and the gate of the isolation transistor are connected to a clock signal. The SEU immune storage cell has a first access node and a second access node. The first access node is complementary to the second access node. The first access node is connected to the precharge transistor and the second access node is connected to the isolation transistor. The invertor is coupled between the precharge transistor and the isolation transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.