PCI bus system wherein target latency information are transmitted along with a retry request
US6282598A · kind A · utility
13Cited by
9References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 17, 1998 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Apr 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/362
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a PCI bus system comprising an initiator and a target, wherein data is transferred from the target via a PCI bus in response to access from the initiator, a time intercal period required from access to data transfer is stored as latency information in the target. The latency information is transferred from the target to the initiator in response to access requests from the initiator. The initiator determines the next access timing from the relevant latency information. Thereby, a PCI bus occupation time due to repeated access requests can be shortened.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.