Memory controller and method for meory devices with mutliple banks of memory cells
US6282604A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 20, 2000 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Sep 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0882
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is used in conjunction with a plurality of dynamic memory devices (DRAM's). Each DRAM device has a plurality of adjacent dependent banks of memory cells. The memory controller has a cache. Each entry in the cache corresponds to one bank in one of the dynamic memory devices, and stores information indicating which of the dynamic memory devices the entry corresponds to, whether the bank to which the entry corresponds is open, and which row of the bank was last accessed. Bank status lookup logic is used to access cache entries in response to a memory access request that includes a bank address, a device address and a row address. The bank status lookup logic retrieves an entry, if any, in the cache corresponding to the device address and bank address. It also simultaneously retrieves entries, if any, in the cache for banks physically adjacent to the bank identified by the device address and bank address. Reduction logic converts the information in the retrieved cache entries into a selection signal, and a protocol state machine lookup outputs a sequence of control signals in accordance with the selection signal. The control signals are sent to the dynamic memory de…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.