System, method, and program for detecting and assuring DRAM arrays
US6282622A · kind A · utility
Inventor
Key dates
| Filing date | Aug 10, 1998 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Aug 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method, and program for detecting and assuring a row by column structure in a Dynamic Random Access Memory array is disclosed. By writing to and reading from each memory location of the DRAM array, memory integrity is assured. The number of columns in the DRAM array is identified by writing data to and reading data from addresses selected from a series of cell addresses. The series of cell addresses identify standard DRAM column structures. When the data written to and read from the cell address is identical, the column configuration of the DRAM arrays is identified. The number of rows in the memory array is then identified by writing data to and reading data from addresses selected from a second series of cell addresses. The second series of cell addresses identify standard DRAM row structures. When data written to and read from the cell address is identical, the row configuration of the DRAM array is identified and accordingly, the row by column structure and integrity of the DRAM array are known.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.