Method and processor for structuring a multi-instruction computer program in an internal directed acyclic graph
US6282708A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 1999 |
| Grant date | Aug 28, 2001 |
| Priority date | — |
| Expiry date | Feb 25, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/433
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for structuring a multi-instruction computer program as containing a plurality of basic blocks, that each compose from internal instructions and external jumps organised in an internal directed acyclic graph. A guarding is executed on successor instructions that each collectively emanate from a respectively associated single predecessor instruction. A subset of joined instructions that converge onto a single join/target instruction are then unconditionally joined. This is accomplished by letting each respective instruction in the subset of joined instructions be executed under mutually non-related conditions, specifying all operations with respect to a jump instruction, specifying all operations that must have been executed previously, and linking various basic blocks comprising subsets of successor instructions in a directed acyclic graph which allows parallel execution of any further subset of instructions contained therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.