Method of reducing RIE lag for deep trench silicon etching

US6284666A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Munir D. Naeem · Poughkeepsie, US
• Gangadhara S. Mathad · Poughkeepsie, US
• Byeong Y. Kim · Lagrangeville, US
• Stephan Kudelka · Radeberg, DE
• Brian Lee · New York, US
• Heon Lee · Sunnyvale, US
• Elizabeth C. Morales · Poughkeepsie, US
• Young Jin Park · Suwon-si, KR
• Rajiv Ranade · Fishkill, US

Key dates

• Filing date: May 31, 2000
• Grant date: Sep 4, 2001
• Expiry date: May 31, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3065
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., <30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures.