Chip scale packaging technique for optical image sensing integrated circuits
US6285064A · kind A · utility
132Cited by
1References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 28, 2000 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Mar 28, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A chip scale packaging for optical image sensor integrated circuits is disclosed. Micro lenses are placed on top of a wafer having the image sensors formed thereon. An adhesive matrix is placed atop of the wafer. The adhesive matrix has openings that align with the micro lensed sensor array on top of the wafer. A cover glass is then placed over the adhesive and the adhesive is activated to secure the cover glass to the wafer. Because the adhesive has openings above the micro lensed portion no distortion or reduction of the lens effect is caused by the adhesive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.