Dynamic logic circuits with reduced evaluation time
US6285217A · kind A · utility
0Cited by
8References
12Claims
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Key dates
| Filing date | Sep 8, 1999 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Sep 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dynamic logic circuits with reduced evaluation time provide faster output in dynamically evaluating logic circuits by increasing the rate of change of the voltage at the junction of logic input ladders. The circuits use a cross-coupled amplifier to charge the input ladder combining node once the node begins to evaluate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.