Sample-and-hold device
US6285220A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2000 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Aug 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A sample-and-hold device comprises a sampling transistor (Q.sub.ech) and a sampling capacitor (C.sub.ech), the sampling transistor being off in hold mode in order to prevent the discharging of the sampling capacitor and conductive in sampling mode to apply a voltage to the capacitor that is substantially equal to the voltage (V.sub.ech) at its base. In order to apply a cut-off voltage to this base, in off mode, that is equal to the voltage present at the sampling capacitor, there is provided a circuit comprising, in series, between two power supply terminals, two MOS type transistors (MP1, MP2) having drain-source channels substantially with the same width-to-length ratio, a bipolar transistor (Qcl) having its base connected to the junction point of the two MOS transistors and its emitter connected to the base of the sampling transistor (Q.sub.ech), and a diode (D1) biased by a current (Ip), connected between the source and the gate of one of the two MOS transistors (MP1), the gate of the other transistor (MP2) being connected to the sampling capacitor. This device can be applied especially to samplers used upline to an analog-digital converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.