Method and apparatus for hardening a static random access memory cell from single event upsets
US6285580A · kind A · utility
13Cited by
23References
26Claims
0Family size
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Key dates
| Filing date | Nov 17, 1999 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Nov 17, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single event upset hardened memory cell to be utilized in static random access memories is disclosed. The single event upset hardened memory cell includes a first set of cross-coupled transistors, a second set of cross-coupled transistors, and a set of isolation transistors. The set of isolation transistors is coupled to the first set of cross-coupled transistors such that two inversion paths are formed between the cross-coupled transistors and the isolation transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.