MRAM having semiconductor device integrated therein
US6285581A · kind A · utility
39Cited by
10References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1999 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Dec 13, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetic memory cell (10) has a semiconductor layer (12) positioned between first (11) and second (13) ferromagnetic layers forming either a p-n or Schottky junction. A magnetic layer (34) is positioned between the first ferromagnetic layer and a digit line (first) for pinning a magnetic vector within the second ferromagnetic layer. In a 13 embodiment, a gate contact (37) is spaced apart from the layer of semiconductor material for controlling the electron flow through the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.