Memory cell string structure of a flash memory device
US6285587A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 13, 2000 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Jun 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device includes a memory cell array divided into a plurality of memory blocks. A plurality of bit lines are arranged through the plurality of memory blocks, and a plurality of word lines are arranged in each of the memory blocks so as to intersect the bit lines. Each of the memory blocks includes a plurality of memory cell strings corresponding to the bit lines. Each memory cell string includes a first string segment having a plurality of EEPROM cells and a second string segment having a plurality of EEPROM cells. A first select transistor connects the first string segment to a corresponding bit line in response to a first select signal. A second select transistor connects the first string segment to the second string segment in response to a second select signal. And a third select transistor connects the second string segment to a common source line in response to a third select signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.