Multi-level type nonvolatile semiconductor memory device
US6285596A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 2000 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Oct 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/691
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device having nonvolatile memory cells, each of said memory cells including a semiconductor substrate of one type of electric conduction, a pair of source and drain regions of the opposite type of electric conduction formed in the semiconductor substrate, an electric charge-capturing film formed on a channel region between the pair of source and drain regions, and a gate electrode formed on the charge-capturing film and working as a control electrode. The electric charge-capturing film has a multi-layer structure in which at least four insulating films and at least three dielectric films each working as an electric charge accumulation layer are alternatingly laminated one upon the other, the lowermost insulating film among the at least four insulating films is formed as a gate-insulating film, a plurality of different threshold voltages are set to the at least three dielectric films to correspond to their electric charge-capturing states, and at least four kinds of memory states are specified depending upon the plurality of threshold voltages. This constitution makes it possible to easily and reliably adjust the amount of electric charge to be cap…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.