Memory system
US6285607A · kind A · utility
76Cited by
3References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2000 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Oct 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system (10) incorporating a plurality of memory devices (42) at least one of which has a defective location. Defects are mapped in a non-volatile memory (46). Data structures are divided into portions which are respectively stored in different ones of the memory devices (42). The controller (17) of the system accesses the non-volatile memory so as to generate on a per device basis an address corresponding to a non-defective location in that device. In this system, different addresses may therefore be applied to different ones of the devices (42) when a data structure is written to or read from the memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.