Hardware verification tool for multiprocessors
US6285974A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1999 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | May 4, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One aspect of the invention relates to a method for detecting architectural violations in a multiprocessor computer system. In one version of the invention, the method includes the steps of generating a testcase instruction stream having a plurality of instructions, executable by the processors, which access a memory which is shared by the processors; detecting dependent instructions in the testcase instruction stream; and modifying the testcase instruction stream by inserting logging instructions in the testcase in the testcase instruction stream which cause data associated with observable instructions to be written to a logging memory by writing a first sequence of unique monotonically increasing values to the memory. Thereafter, a second sequence of values is read from the memory location and a window of observed values is defined, wherein the window has a highest observable value and a lowest observable value where the highest observable value is set to the highest value of the first sequence and the lowest observable value is set to the lowest value of the first sequence and wherein the lowest observable value is updated with a next observable value from the first sequence whe…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.