High efficiency digital filter using sequential multiply and add operations
US6286019A · kind A · utility
2Cited by
7References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1999 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Sep 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0685
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for optimizing the design of a digital filter for use in a microprocessor that utilizes sequential multiply and add instructions as distinct from single multiply and accumulate cycles. The method involves alternating the steps of multiplying and adding samples of the input signal and the coefficients that are assigned to the corresponding samples of the input signal. This add and multiply sequence is more efficient on most general-purpose computers than the more common load, multiply, add sequence used for this type of filter operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.