Advanced read cache emulation
US6286080A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low complexity approach to DASD cache management. Large, fixed-size bands of data from the DASD, rather than variable size records or tracks, are managed, resulting in reduced memory consumption. Statistics are collected for bands of data, in order to improve upon the performance of a simple LRU replacement scheme. The statistics take the form of a single counter which is credited (increased) for each read to a band and penalized (reduced) for each write to a band. Statistics and LRU information are also collected for at least half as many nonresident bands as resident bands. In an emulation mode, control information (e.g., statistics and LRU information) regarding potentially cacheable DASD data, is collected even though there is no cache memory installed. When in this mode, the control information permits a real time emulation of performance enhancements that would be achieved were cache memory added to the computer system. Dynamic reconfiguration of the cache size is also permitted in real time without requiring computer system downtime.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.