Paged based memory address translation table update method and apparatus
US6286092A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1999 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | May 12, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1081
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A page based memory address translation table update method and apparatus uses a first processor, such as a host processor or other processor, to notify a second processor to update its own page table. In one embodiment, the first processor generates an execution order driven page table maintenance command for the second processor. The second processor updates its own page table in sequence with received embedded commands. The second processor also updates its own translation look aside buffer in response to the page table maintenance data generated by the first processor. The page table maintenance data may be, for example, a page table maintenance command that is queued by the first processor so that the table update for the second processor is deferred from the first processors point of view since the second processor performs its own page table edits based on the order in which the page table maintenance command appears in a command queue for the second processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.