Memory architecture for automatic test equipment using vector module table
US6286120A · kind A · utility
6Cited by
11References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 1, 1994 |
| Grant date | Sep 4, 2001 |
| Priority date | — |
| Expiry date | Sep 1, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31921
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A tester having a fast but flexible pattern generator which is implemented using readily available memories. The tester includes a pattern memory which holds test vectors. The vectors are organized into modules. The order of execution of the modules is selected from a list stored in memory. In the preferred embodiment, memories which operate in burst mode are used to implement the pattern memory. To compensate for the decrease in data rate which occurs when execution switches between modules in the middle of a burst, the memory refresh rate is dynamically altered upon switching between modules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.