Thin film transistor manufacturing method
US6287898A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 3, 1999 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Jun 3, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
Abstract
After a polycrystalline silicon film is formed on a glass substrate, the first gate insulating film is formed on the polycrystalline silicon film and the polycrystalline silicon film and the first gate insulating film are patterned into a island shape. Next, impurities are doped into the polycrystalline silicon film through the first gate insulating film using a resist mask, thereby forming the first source-drain region in part of the polycrystalline silicon film. Further, the second gate insulating film is formed on the first gate insulating film and a gate electrode is formed on the second gate insulating film. Thereafter, impurities are lightly doped through the first and second gate insulating films to thereby form the second source-drain region. Thus, no high etching technique is required for the manufacture of a thin film transistor and occurrence of electrostatic damage to the gate insulating films is prevented, to thereby make it possible to improve production yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.