Integrated circuit and method
US6287924A · kind A · utility
80Cited by
15References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1999 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Sep 28, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Sidewall spacers extending above a silicon gate with the distance between the spacers exceeding the length of the gate are used to confine selective silicon growth of the gate and subsequent self-aligned silicidation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.