Composite gate structure memory cell having increased capacitance
US6288423A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 14, 1998 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Apr 14, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
Abstract
A semiconductor device of the present invention is a semiconductor memory having a charge storage film. Recesses or holes which effectively increase the capacitance of a floating gate or a memory cell capacitor are formed in the charge storage film. These recesses or holes are formed at the same time the floating gate electrode or the lower electrode of the capacitor is isolated into the form of islands. A dielectric film and a polysilicon film is formed on the isolated island floating gate electrodes or lower electrodes. These recesses or holes increase the surface area of the dielectric film and improve the write and erase characteristics of a memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.