Active fail-safe detect circuit for differential receiver
US6288577A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 2001 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Mar 2, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A fail-safe circuit for a differential receiver can tolerate high common-mode voltages. An output from a differential amplifier that receives a V+ and a V- differential signal can be blocked by a NOR gate when the fail-safe condition is detected, such as when the V+, V- lines are open. Pullup resistors pull V+, V- to Vcc when an open failure occurs. A pair of comparators receive a reference voltage on the non-inverting input. Once comparator outputs a high when the V+ line is above the reference voltage, and the other comparator outputs a high when the V- line is above the reference voltage. When both V+ and V- are above the reference voltage, the NOR gate blocks the output from the differential amplifier, providing a fail-safe. Since the reference voltage is very close to Vcc, a high common-mode bias can exist on V+, V- without falsely activating the fail-safe circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.