CMOS pulse shrinking delay element with deep subnanosecond resolution
US6288587A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1999 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Apr 7, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/159
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS pulse shrinking delay element with deep subnanosecond resolution applicable to a Time-to-Digital Converter (TDC) can control its pulse shrinking or expanding capability be adjusting the dimension ratio between internal adjacent elements. This eliminates the need in prior CMOS pulse shrinking delay elements to adjust an external bias voltage or continuously calibrate the element in order to control pulse shrinking or expanding capabilities, facilitates simplification of circuits using the delay element, permits more precise design and control of the pulse shrinking or expanding capabilities of every element in a TDC circuit, and in practice reduces single shot errors in a cyclic TDC utilizing the pulse shrinking delay element to on the order of ten picoseconds, resulting in a TDC having extremely fine resolution, excellent accuracy, low power consumption, and low sensitivity to supply voltage and ambient temperature variations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.