Gate biasing arrangement to temperature compensate a quiescent current of a power transistor
US6288596A · kind A · utility
6Cited by
8References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 24, 2000 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Jan 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To eliminate the temperature dependency of the quiescent current of a power transistor (1), the gate bias voltage of the power transistor (1) is controlled by means of the output voltage of a biasing transistor (3) residing on the same silicon chip as the power transistor (1), and by interconnecting the gate (G3) and drain (D3) of the biasing transistor (3) and feeding it with a constant current (IB) from external circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.