MOS buffer immun to ESD damage
US6288884A · kind A · utility
9Cited by
3References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 8, 1999 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Jun 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/911
Abstract
A buffer is integrated with an ESD protection circuit onto a semiconductor substrate. The ESD protection circuit is triggered by means of a MOS-like device having a first spreading resistance during an ESD event. The buffer includes a plurality of finger-type devices connected in parallel, where each finger-type device is provided with a second spreading resistance less than the first spreading resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.