Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks
US6288941A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1995 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Jan 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electrically erasable semiconductor nonvolatile memory device has an array of memory cells arranged in rows and columns and one or more information erasure signal generating circuits. Each of the memory cells of the memory cell array includes a field-effect transistor element having a control gate connected with a word line conductor extending in a direction of the rows, a floating gate where carriers may be accumulated, a drain connected with a data line conductor extending in the direction of the columns and a source connected with a source conductor. The memory cell array may be divided into a plurality of memory blocks so as to have boundaries in the row direction or in the column direction, with the source conductors arranged in the row direction or in the column direction. Information erasure signals may be supplied to the source conductors or data line conductors with a time delay therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.