Wired address compare circuit and method
US6288948A · kind A · utility
1Cited by
4References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first register, a second register and a plurality of compare circuits. The first register may be configured to store a plurality of first address bits. The second register may be configured to store a plurality of second address bits. The plurality of compare circuits may each be configured to generate an output signal in response to one of said plurality of first address bits and one of said plurality of second address bits. The output signals are generally each at either (i) the same logic state or (ii) a high-Z state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.