Controlling the precharge operation in a DRAM array in a SRAM interface
US6288959A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2000 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Aug 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The precharge operation of a DRAM array in a non-multiplexed address interface is controlled so that the DRAM is precharged only if there is a change in the word line address. By precharging the DRAM only when a new word line is asserted, a significant power savings may be obtained. An activity monitor compares each new word line address with the previous word line address. If the activity monitor indicates that a new word line is asserted, a timing control circuit will precharge the DRAM, including equalizing the bit lines. If the activity monitor indicates that the word line is not changed, the timing control circuit does not precharge the DRAM. The timing control circuit includes a dummy precharge circuit and initiates a dummy precharge cycle in the beginning of each new cycle for timing purposes. The timing control circuit initiates the active cycle after the dummy precharge cycle regardless of whether a new word line is asserted or not.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.