Bias circuit for read amplifier circuits for memories
US6288960A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 11, 2000 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Oct 11, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bias circuit for read amplifier circuits for memories includes at least one first circuit branch formed by a first pair of MOS transistors connected between a supply voltage and ground. The first pair of MOS transistors includes a P-channel diode connected transistor and an N-channel transistor connected in series, with an enable transistor interposed therebetween. The first circuit branch drives a capacitive load for coupling to the supply voltage. The bias circuit further includes reference current amplifier circuit branches for amplifying a reference current which flows in the first circuit branch for charging the capacitive load. A circuit portion, which controls the charging current of the capacitive load, includes a feedback loop between the reference current amplifier circuit branches and the capacitive load.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.