Scaleable low-latency switch for usage in an interconnect structure
US6289021A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 20, 1998 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Jan 20, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5684
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A scalable low-latency switch extends the functionality of a multiple level minimum logic interconnect structure for usage in computers of all types, networks and communication systems. The multiple level minimum logic interconnect structure employs a data flow technique based on timing and positioning of messages moving through the structure. The scalable low-latency switch is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided while the interconnect structure operates as a "deflection" or "hot potato" system in which processing and storage overhead at each node is reduced. The interconnect structure using the scalable low-latency switch employs a method of achieving wormhole routing through an integrated circuit chip by a novel procedure for inserting messages into the chip. Rather than simultaneously inserting a message into each unblocked node on the outer cylinder at every angle, messages are inserted simultaneously into two columns A and B only if an entire message fits between A and B. Messages are inserted into column 0 at time 0. Messages are inserted into colum…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.