Method and apparatus for recentering an elasticity FIFO when receiving 1000BASE-X traffic using minimal information
US6289066A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1998 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Jun 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/352
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus is provided that solves the problem of data overrun and underrun, for example in a system that exchanges data using the Gigabit Ethernet protocol. A single 8-bit data path is provided as output and the main protocol state machines are kept running in the clock domain of the rest of the circuit, after an elasticity FIFO, so that no additional synchronization is necessary. The invention makes no demands upon the receive clock other than those specified in the relevant standard for duty cycle and accuracy. The invention correctly combines the two effective data streams back into a single data stream, only modifying the FIFO when it is acceptable to do so, and in a way that does not corrupt data packets passing through the FIFO. By providing a minimal set of logic running in the receive clock domain, it is possible to simplify the design of the main protocol state machines. Only a very small portion of the design must be aware of the dual-clock nature of the physical interface. In addition, because all key state machines are no longer in the receive clock domain, any state information or registers are available even if the receive clocks are not running correctly…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.