Computer-assisted design analysis method for extracting device and interconnect information
US6289116A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1997 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Sep 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for extracting design information from a semiconductor integrated circuit (IC) or at least a portion thereof comprising the steps of: (a) imaging at least a portion of one or more IC layers to obtain stored images of said portions of the IC; (b) using manual or automatic registration techniques to mosaic images; (c) using an IC layout package possessing a feature of allowing images to be displayed and moved and polygons to be created to allow the recreation of the IC layout in the form of polygons; (d) exporting or storing of a polygon database in a standard IC layout format; (e) creating a table of transistor connections (netlist); (f) organizing circuit netlist into functional blocks of increasing complexity; and (g) generating a schematic diagram.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.