Operand supply to an execution unit
US6289417A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 1998 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | May 18, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/383
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor system comprising a register bank 6 and an execution unit 8 incorporating a barrel shifter 10 and an ALU 12 is provided. The register bank 6 has X read ports whilst at least some of the program instructions require Y input operands to be read from the register bank 6, where Y is greater than X. A cache register 18 is provided that caches previously read input operands for supply to the barrel shifter 10 and if it is detected that the same register is being read a second or subsequent time then this cached value is supplied to the barrel shifter 10 rather than requiring a further read from the register bank 6. A tag register 20 associated with each cache register 18 draws data indicating from which register within the register bank 6 the cached data value was copied. A valid flag 22 indicates that that cached data value is still current, i.e. at the corresponding register within the register bank 6 has not been overwritten.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.