Hardware-software co-synthesis of hierarchical heterogeneous distributed embedded systems
US6289488A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 1998 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Feb 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware-software co-synthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules such that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium-to-large scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the co-synthesis system, may itself be non-hierarchical or hierarchical. Traditional non-hierarchical architectures create communication and processing bottlenecks, and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives. The present invention addresses the problem of hardware-software co-synthesis of hierarchical heterogeneous distributed embedded system architectures from hierarchical or non-hierarchical task graphs. The co-synthesis algorithm has the following features: 1) it supports periodic task graphs with real-time constraints, 2) it supports pipe…
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