Optimization of integrated circuit properties through constraints using a dominant time constant
US6289490A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1998 |
| Grant date | Sep 11, 2001 |
| Priority date | — |
| Expiry date | Oct 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimizing an integrated circuit uses a dominant time constant of a transition of the circuit. A physical layout of the circuit is characterized in terms of design parameters. The circuit is modeled by a conductance matrix G and a capacitance matrix C, wherein G and C are affine functions of the design parameters. The optimization method comprises the step of finding the values of the design parameters that optimize a property of the circuit while simultaneously enforcing a constraint that the dominant time constant must be less than a maximum value t.sub.max. Mathematically, the constraint on the dominant time constant can be written: t.sub.max G-C.gtoreq.0. The optimization method can be used when the circuit has a non-tree topology. Furthermore, when the design parameters comprise variables that relate to sizes of elements of the circuit, a topology of the circuit is optimized by the optimization method. In some embodiments the circuit is optimized for a plurality of transitions, and in some embodiments the design parameters are subject to design constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.