Method for fabricating ferroelectric memory
US6291251A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2000 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Jun 7, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/945
Abstract
Method for fabricating a nonvolatile ferroelectric memory, including the steps of (1) forming an insulating layer, a semiconductor layer, an etch stop layer, a lower electrode, a ferroelectric layer, and an upper electrode on a substrate in succession, (2) forming an etch mask pattern of a required form on the upper electrode, (3) using the etch mask pattern as a mask in subjecting the upper electrode, the ferroelectric layer, the lower electrode, the etch stop layer, the semiconductor layer, and the insulating layer to en bloc etching, to expose the substrate, and (4) removing the etch mask pattern, and forming source/drain regions in the exposed substrate, whereby providing a simple fabrication process and permitting to minimize an alignment allowance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.