Method for implementing resistance, capacitance and/or inductance in an integrated circuit
US6291305A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1999 |
| Grant date | Sep 18, 2001 |
| Priority date | — |
| Expiry date | Jun 11, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
On-chip resistance, capacitance and/or inductance is implemented in an integrated circuit in vertical configurations using stacked vias and medullization layers within the integrated circuit. Column shaped openings or vias are formed within the integrated circuit and connect from a silicon substrate to various metal traces. The vias are filled with conductive material such as platinum or tungsten. Parallel vias are used to form capacitance, while multiple vias and metal traces are arranged in various patterns over several planes in order to form resistance and/or inductance. The use of the stacked vias and metal traces in a vertical fashion reduces lateral spacing required to implement on-chip resistance, capacitance and/or inductance and allows for more efficient use of space in very large scale integration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.